How to Amplify AC Signals With Large DC Offset Using Indirect Current Mode Instrumentation Amplifiers?
How to support applications with large differential offset voltages without adding gain stages?
This can be accomplished by designing an AC coupling and gain solution using a micropower rail-to-rail indirect current mode instrumentation amplifier in one stage. This article will outline the advantages of this design and provide step-by-step design guidance.
In applications such as electromagnetic flow meters and bioelectrical measurements, small differential signals are in series with much larger differential offsets. These offsets often limit the gain a circuit can achieve in a front-end design, affecting the overall dynamic range. Gain limiting is more challenging when using lower supply voltages, such as in battery-powered signal chains. One solution to this large differential offset problem is to use an AC-coupled measurement signal chain. A typical AC-coupled signal chain consists of a low-gain instrumentation amplifier, followed by a high-pass filter and additional gain stages (see "Amplifying AC Signals with Large DC Offsets to Support Low-Power Designs"). In most applications, it is best to get as much gain as possible in the first stage because this helps improve the referred-to-input (RTI) noise of other gain stages in the signal chain. This article describes the design and implementation of an indirect current mode instrumentation amplifier architecture to achieve high gain and AC coupling in one stage. The design uses the AD8237 micropower, zero-drift instrumentation amplifier with wide common-mode and differential input ranges. Other examples of indirect current mode architectures are the AD8420. The main benefits of this indirect current feedback include:
Low power architecture
No diamond plot limitations like other typical architectures such as instrumentation amplifiers consisting of two or three op amps
Good gain drift performance can be achieved using external resistor matching
Achieve high CMRR without relying on resistor matching
High impedance reference pin
The overall schematic is provided for the circuit shown in Figure 1, in which the AD8237 indirect current-mode instrumentation amplifier was selected. However, to achieve high gain and AC coupling in one stage, an integrator circuit must be implemented in the AD8237's feedback loop. This solution provides greater gain than an instrumentation amplifier solution consisting of two or three op amps, which removes the offset after applying the gain. For the proposed architecture, offset correction occurs before the gain stage, so the instrumentation amplifier can have large gain. Both architectures are described in the appendix. The ADA4505 op amp is used as an integrator circuit in the feedback loop. The AD8237's output is sensed by the integrator input and drives the AD8237's reference pin, forcing the AD8237's output to VMID, which is set at the positive input of the ADA4505. Even if the integrator circuit provides a low-pass filter function, in this case the overall circuit will have a high-pass filter transfer function due to its use in the feedback loop. Because of this behavior, not only does it end up blocking any DC offset before applying the gain, thus providing greater gain than other solutions, but it is more helpful with low supply voltages and large offsets because the remaining operating margin Quantity is very limited. The integrator circuit also forces the output of the AD8237 to a selected voltage through the reference pin. In effect, the integrator forces the voltage at the reference pin relative to the AD8237's FB pin to be equal to the input differential voltage, but in the opposite direction.
Figure 1. AC-coupled signal conditioning circuit using indirect current mode architecture
Design specification example
Low-power applications typically use a single power supply, with supply voltages typically between 1.8V and 3.6V. Design choices for the circuit shown in Figure 1 depend on the amplitude range and frequency of the input signal and offset. Table 1 lists example design specifications for the circuit shown in Figure 1.
The design choice for this circuit was made with the AD8237 using a low bandwidth mode in order to increase gain flexibility and stability.
Table 1. Key design specifications for the circuit shown in Figure 1
The circuit shown in Figure 1 consists of the AD8237 micropower, rail-to-rail instrumentation amplifier and the ADA4505 zero-input crossover distortion operational amplifier. Both devices can be powered from a minimum 3.3V supply, VDD.
This circuit can output a voltage VOUT, which represents the amplified signal of the AC signal VSIGNAL at the input end after removing the DC offset voltage VOFFSET. The VMID voltage generated by this circuit is used to set the common mode of the positive input of the ADA4505 and the output of the AD8237 gain stage to the mid-supply voltage. VMID is generated by a voltage divider (R1, R2) and buffered by another ADA4505. The AD8237 is available in a ultra-small package (MSOP) and the ADA4505 is available in a compact wafer-level chip-scale package (WLCSP).
1. The positive input VMID of the ADA4505-2 (1/2) will set the value of VREF (the reference pin of the AD8237), which sets the output VOUT. Given the relationship between common-mode input voltage and output range, or the diamond plot, the optimal value for most instrumentation amplifiers is mid-supply voltage (+VDD/2) to ensure maximum output swing between the two supply rails. The Design Simulation section introduces a diamond diagram tool that can help with this.
2. The selection of resistor values R1 and R2 is also important when considering the total supply current of the circuit. Resistor selection is a trade-off between noise and power dissipation. For this circuit, it is best to choose a larger resistor value to minimize additional supply current. For this resistor divider, the additional supply current added will be:
For the resistor divider (R1, R2), a capacitor C1 can be added to band limit the noise and reduce 50 Hz/60 Hz or other interference to VDD. The larger the capacitor, the better the noise filtering; however, it takes longer for the VMID to stabilize on power-up. The time required to establish within 1% is estimated as:
3. Tolerances should be considered when selecting passive component values (resistors and capacitors). For the resistor divider (R1, R2), the target VMID value may shift, which affects the output swing range VOUT of the AD8237 and ADA4505.
From the circuit shown in Figure 1, we can see that the transfer function will have two cutoff frequencies, which are the result of the high-pass filter from the ADA4505 integrator circuit in the feedback and the low-pass filter response due to the bandwidth of the AD8237. This may introduce some gain error, which is related to the cutoff frequency of the integrator (ADA4505) and the bandwidth of the AD8237. Therefore, the high-pass cutoff frequency and low-pass cutoff frequency must have a certain range. Depending on how close the cutoff frequencies are to each other, the gain error percentage may change.
4. If the application requires the use of a high impedance sensor, a buffer such as the ADA4505 can be used before the AD8237 input to provide higher input impedance and lower input bias current, since the buffer will convert the high impedance input to a low Impedance output. The AD8237 has a maximum input bias current of 1nA over temperature.
1. Voltage divider used to set VMID:
According to point 2 of "Design Considerations", for the circuit in Figure 1, the values of the peripheral components are set to R1 = R2 = 1MΩ so that the supply current contribution remains around 1µA.
Output of resistor divider before ADA4505:
Assuming a 5% tolerance for R1 and R2 and accounting for the ADA4505 offset:
In order to eliminate AC power interference and noise from the resistor, set C1 so that the cutoff frequency is at least 20Hz less than the VSIGNAL lowest frequency. Note that the capacitor value can be larger if further band limiting of the noise is required.
In this case, C1 is set to 22nF, which provides a frequency of:
2. Instrumentation amplifier (AD8237) gain value VSIGNAL:
Consider that the electromagnetic flow sensor output typically ranges from ±75µV to ±6mV peak-to-peak signal amplitude. For the circuit shown in Figure 1, the peak-to-peak signal amplitude range will be set to VSIGNAL = 6mV peak at 30Hz.
Then, consider the limitations of the AD8237 output swing range on the supply rails. These values can be found in the "Output Swing" section of the data sheet. To be conservative, let’s first use the RL = 10kΩ swing at +25°C:
For 3.3V power supply:
Since the output is fully differential, the worst-case swing of the output relative to VMID will be:
For positive input signal (=1.732V):
For negative input signal (=1.568V):
Now to set the gain, calculate the total expected differential input signal and use the lower bounds of the positive and negative swing ranges to set the maximum swing range:
Taking into account the output voltage range limitation, the AD8237 gain should be less than 253. To allow some margin for DC errors and other factors, the gain value of the circuit shown in Figure 1 should be less than the maximum value. There is also a trade-off between gain and settling time: the higher the gain, the slower the filter's time constant. Due to the above considerations, the AD8237 gain is set to 101.
Please note the benefits of Design Considerations Step 1 to maximize the swing value.
It can be seen from the data sheet that the relevant formula for gain is:
The AD8237 data sheet provides recommended resistor values for different gain selections. For a selected gain of 101, the values of these resistors should be: RF1 = 1kΩ, RG1 = 100kΩ.
3. Instrumentation amplifier (AD8237) bandwidth:
From the data sheet, we know that the cutoff frequency value is
If the design specifications require some minimum attenuation at the maximum signal frequency, this is easy to check for a given filter cutoff frequency.
4. Set the high-pass filter cutoff frequency:
As mentioned in the "Design Considerations" section, the high-pass filter cutoff frequency set by the integrator may be too close to the low-pass filter cutoff frequency set by the AD8237 bandwidth. This will introduce some gain error into the previously determined gains.
Assuming a tolerance of ±5% for R3 and C3, the fastest time constant should be less than the VSIGNAL lowest frequency:
Resistor R3 will have a constant value of 1 MΩ to minimize the current entering the op amp through this resistor.
Select the closest standard capacitor value, the cutoff frequency is approximately 20 Hz, and set C3 = 1.5 µF, so the updated cutoff frequency is:
If the design specifications require some minimum attenuation at the minimum signal frequency, this is easy to check for a given filter cutoff frequency. See an example of this circuit:
5. Offset voltage:
Both signals VOFFSET and VCM have limits.
As expected, the DC offset can be larger than typically found in most applications. In this case, the voltage value must be VOFFSET ≤ ±VMID. If the DC offset is greater than this limit, the VREF voltage value will exceed the supply voltage range of the ADA4505. The formula related to the reference pin is: VREF = VMID – VOFFSET. VOFFSET will be set to 1V.
As for the common mode voltage, it is directly related to the VOFFSET value since VCM must be within the range:
If these limits are not verified, the input values to the AD8237 are above or below the supply voltage range. VCM will be set to 1.65V.
To examine an instrumentation amplifier's common-mode input range versus output voltage, or diamond plot, the supply voltage +VDD, reference voltage, gain, common-mode swing, and differential input swing are required. Analog Devices' Instrumentation Amplifier Diamond Plot tool can help understand whether the input swing is within the operating range of the device. Note that the output swing used by this tool uses worst-case load conditions (minimum resistive load). Therefore, if designed to the tool's limits, the system will have more margin for larger resistive loads. Looking at the results in Figure 2, the purple outline is the usable range of the AD8237 given the supply voltage, output swing, input common-mode range, and device reference voltage. The red outline shows how much of the available range is used for a given common-mode and differential input mode swing. The goal is to keep the red outline within the purple outline. If certain conditions violate this requirement, the tool will display an error and provide suggestions. It is important to note that in this tool it is not possible to implement an integrator circuit in a feedback loop. But there is a workaround, and that is to configure the diamond input signal as if the circuit's VOFFSET and VCM voltages were added (in Figure 1). This allows the use of spacing (0.65V to 2.65V) since the DC offset is eliminated and not amplified. It also shows that the common-mode voltage can be higher because there is still some headroom in the output swing. To further understand what is happening inside the instrumentation amplifier, the Internal Circuitry tab displays the voltages at the internal nodes.
Figure 2. AD8237 Diamond Plot Tool Example
LTspice® is an excellent simulation tool for checking previously performed design process calculations, including other meaningful specifications such as noise performance over the target signal band. The LTspice schematic is shown in Figure 3. The first simulation (Figures 4 and 5) is a transient simulation with a DC offset of 1V and an input signal of ±6mV (30Hz). Figure 4 shows the signals at different stages in the circuit. Figure 5 is a larger version of Figure 4 with the circuit set up and the integrator capacitor charged to its final value. The blue curve is the output of the AD8237's integrator or reference pin. The red curve is the VMID value (equal to VDD/2), and the green curve is the amplified final 30Hz output signal VOUT.
Figure 3. LTspice schematic diagram
Figure 4. Transient simulation results
Figure 5. Magnified view of transient simulation results
Table 2 shows a comparison of the design goals and transient simulation results. For the maximum and minimum VOUT values, the expected values are from: VOUT = VMID ± VSIGNAL × 101; in this case, the expected values are equal to 2.256V and 1.044V. The expected value of VREF is equal to VMID – VOFFSET, which in this case is 0.65V. VMID is equal to the mid-supply voltage, which in this case is 1.65V.
Table 2. Design goals and simulation transient analysis
The results obtained in the transient analysis are very similar to the expected results in terms of voltage output. However, due to the large integrator capacitance and the achieved DC offset, it took 17 seconds for the simulation to set up and for the output to reach its final value. This settling time comes from the fact that the simulation starts at time 0s and the capacitor needs time to charge to its final value.
Another simulation in Figure 6 shows the frequency response of the circuit in Figure 3 with a DC offset of 1V and an input signal of ±6mV (30Hz). Cursors 1 and 2 in Figure 6 are placed at the -3dB points of the high-pass and low-pass filters respectively. Table 3 shows the comparison of design goals and simulation results.
Figure 6. AC simulation results
Table 3. Design goals and simulation communication analysis
Another simulation in Figure 7 shows the voltage noise density versus frequency RTI for the circuit in Figure 3. This is done by dividing the output noise by the total gain of the solution (101). For the bandpass filter function, the integration frequency interval needs to be selected to calculate the total noise.
Figure 7. Total noise results integrated over the equivalent noise bandwidth
For frequency capping, this would make Use the previously determined maximum frequency value of the sensor, which is 220Hz. For the lower frequency limit, the previously determined minimum frequency value for the sensor will also be used, which is 20Hz. In this case, the resulting noise will be integrated from 20Hz to 220Hz.
The measured noise will actually be higher due to the cutoff frequency of the bandpass filter. The LTspice simulation results assume a brick wall filter with sharp roll-off at 20Hz and 220Hz.
The command line setting in LTspice is: noise V(VOUT) V1 dec 100 20 220. Then hold down the Ctrl key and left-click the waveform name (V(ONOISE)/101). RMS noise can be easily converted to peak-to-peak noise using the following equation:
A quick check of the AD8237 noise and the ADA4505 noise shows that the AD8237 is the dominant noise source.
In order to verify the simulation results, hardware testing can be performed because test boards are provided for both AD8237 and ADA4505. The soldering of each component can be done according to the schematic of the test board. When using both test boards simultaneously, you may need to cut the traces on the AD8237 board to connect the VMID voltage to the RG resistor.
To ensure a better understanding of the results, component values are taken from the design steps section, the same as the design simulation. To simulate electromagnetic flow meters or bioelectrical measurement sensors, different measuring devices can be used, such as voltage calibrators and arbitrary waveform generators.
For this test, the input signal was set to have a DC offset VOFFSET of 1V, a common-mode voltage of 1.65V, and an input signal VSIGNAL of ±6mV (30Hz).
Looking at the results shown in Figure 8, the performance of the output voltage VOUT (yellow curve) is a small voltage difference relative to the expected value, but is still consistent with expectations.
Figure 8. Oscilloscope screenshot, yellow curve corresponds to VOUT and blue curve corresponds to VREF.
Differences between design goals and simulation results may have several causes.
The resistors used have a 5% tolerance, which means the VMID value may be offset.
The test bench setup may have limitations, leading to minor deviations, as shown in the measured simulation results VOFFSET and VSIGNAL.
When acquiring signals from sensors, such as electromagnetic flow meters in field transmitters or electrodes in bioelectrical applications, the signal of interest typically lies above a much larger DC offset. To make it easier to extract relevant information from these sensors, one solution is to implement an AC-coupled measurement signal chain that amplifies the AC signal while eliminating DC offset. An integrator circuit is integrated into the feedback loop, the AD8237 instrumentation amplifier provides the gain, and the AC signal is coupled, all in one stage. By eliminating DC offset at the input stage, this circuit allows signal gain to be applied at the input of the measurement signal chain, minimizing the input-referred noise of the overall measurement solution.
LTspice is a high-performance SPICE III simulation software, schematic acquisition tool and waveform viewer that integrates enhanced features and models to simplify the simulation of switching regulators, linear regulators and signal chain circuits.
Instrumentation Amplifier Diamond Plot Tool
The Diamond Plot Tool is a web application that generates a plot of output voltage range versus input common-mode voltage for a specific configuration, also known as a diamond plot, for Analog Devices instrumentation amplifiers.
Figures 9 and 10 show indirect current mode instrumentation amplifiers and three op amp instrumentation amplifiers. Indirect current mode instrumentation amplifiers provide greater gain than instrumentation amplifier solutions consisting of two or three op amps, which remove offset after applying the gain. For the proposed architecture, offset correction occurs before the gain stage, so the instrumentation amplifier can have large gain. Below is a description of these two architectures.
Figure 9. AD8237 Indirect Current Mode Instrumentation Amplifier Architecture
Figure 10. Three op amp instrumentation amplifier
The indirect current mode instrumentation amplifier in Figure 9 is based on a one-stage configuration. The input voltage is applied to the first GM1 unit, while the GM2 unit is in the feedback loop. Internal integrator amplifier A forces a copy of VIN1 to appear on VIN2. The integrator is used to drive the reference pin before gain. Gain is set by external resistors RFB and RG and is equal to:
The three-op-amp architecture in Figure 10 is based on a two-stage configuration. The first two operational amplifiers U1 and U2, the RGAIN resistor, the R2 resistor and the R1 resistor form a non-inverting amplifier and are considered the input stage. It provides unity common-mode gain, while the differential gain is set by resistor RGAIN and is equal to:
The last op amp U3 and resistor R3 form a differential amplifier that forms the output stage of the instrumentation amplifier. It provides unity differential-mode gain and common-mode rejection. The reference injection point for this architecture is the second stage after applying the first stage gain.
Acknowledgments to the main consultants: David Plourde, IC design engineer in ADI Scientific Instruments (SCI) Department, Aine McCarthy, chief system application engineer in ADI Automotive Department, Tim Green, senior analog application engineer in ADI Scientific Instruments (SCI) Department